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| DS2064 DS2064 8K x 8 Static RAM FEATURES PIN ASSIGNMENT NC A12 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 DQ1 DQ2 GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VCC WE CE2 A8 A9 A11 OE A10 CE1 DQ7 DQ6 DQ5 DQ4 DQ3 * Low power CMOS design * Standby current 50 nA max at 100 nA max at 1 A max at tA = 25C VCC = 3.0V tA = 25C VCC = 5.5V tA = 60C VCC = 5.5V * Full operation for VCC = 4.5V to 5.5V * Data Retention Voltage = 5.5V to 2.0V * Access time equals 200 ns at 5.0V * Operating temperature range of -40C to +85C * Full static operation * TTL compatible inputs and outputs * Available in 28-pin DIP and 28-pin SOIC packages * Suitable for both battery operated and battery backup applications DS2064-200 28-PIN DIP (600 MIL) DS2064S-200 28-PIN SOIC (330 MIL) PIN DESCRIPTION A0-A12 DQ0-DQ7 CE1, CE2 WE OE VCC GND NC - - - - - - - - Address Inputs Data Input/Output Chip Enable Inputs Write Enable Input Output Enable Input 5V Power Supply Input Ground No Connection DESCRIPTION The DS2064 is a 65536-bit low power, fully static random access memory organized as 8192 words by eight bits using CMOS technology. The device operates from a single power supply with a voltage input between 4.5V and 5.5V. The chip enable inputs (CE1 and CE2) are used for device selection and can be used in order to achieve the minimum standby current mode, which facilitates both battery operate and battery backup applications. The device provides fast access time of 200 ns and is most suitable for low power applications where battery operation or battery backup for nonvolatility are required. The DS2064 is a JEDEC-standard 8K x 8 SRAM and is pin-compatible with ROM and EPROM of similar density. 022598 1/9 DS2064 ABSOLUTE MAXIMUM RATINGS SYMBOL VCC VIN, VI/O TSTG TOPR TSOLDER PARAMETER Power Supply Voltage Input, Input/Output Voltage Storage Temperature Operating Temperature Soldering Temperature/Time RATING -0.3V to +7.0V -0.3 to VCC + 0.3V -55C to +125C -40C to +85C 260C for 10 seconds RECOMMENDED DC OPERATING CONDITIONS PARAMETER Power Supply Voltage Input High Voltage Input Low Voltage Data Retention Voltage SYMBOL VCC VIH VIL VDR MIN 4.5 2.0 -0.3 2.0 TYP 5.0 MAX 5.5 VCC + 0.3 0.8 5.5 (tA = -40C to +85C) UNITS V V V V NOTES DC CHARACTERISTICS PARAMETER Input Leakage Current I/O Leakage Current Output High Current Output Low Current Standby Current Standby Current Standby Current Operating Current SYMBOL IIL ILO IOH IOL ICCS1 ICCS2 ICCS2 ICCO CONDITIONS 0V < VIN < VCC CE1=VIH, 0V (tA = -40C to +85C; VCC=5V 10%) MIN TYP MAX +0.1 +0.5 -1.0 4.0 0.5 1 100 70 UNITS A A mA mA mA A nA mA CAPACITANCE PARAMETER Input Capacitance Input/Output Capacitance SYMBOL CIN CI/O MIN TYP 5 5 MAX 10 12 UNITS pF pF (tA = 25C) NOTES 022598 2/9 DS2064 AC CHARACTERISTICS, READ CYCLE PARAMETER Read Cycle Time Access Time OE to Output Valid CE to Output Valid CE or OE to Output Active Output to High-Z from Deselection Output Hold from Address Change SYMBOL tRC tACC tOE tCO tCOE tOD tOH 5 10 5 MIN 200 (tA = -40C to +85C; VCC=5V 10%) TYP MAX UNITS ns 200 100 200 ns ns ns ns 60 ns ns NOTES AC CHARACTERISTICS, WRITE CYCLE PARAMETER Write Cycle Time Write Pulse Width Address Setup Time Write Recovery Time Output High-Z from WE Output Active from WE Data Setup Time Data Hold Time SYMBOL tWC tWP tAW tWR tODW tOEW tDS tDH 5 80 0 MIN 200 150 0 10 (tA = -40C to +85C; VCC=5V 10%) TYP MAX UNITS ns ns ns ns 70 ns ns ns ns 7 7 NOTES TIMING DIAGRAM: READ CYCLE tRC ADDRESSES VIH VIL VIH VIL tOH VIH CE VIL VIH OE VIL tCOE tCOE DOUT SEE NOTE 1 tOD VOH OUTPUT VOH VOL DATA VALID VOL tACC VIH tCO tOD tOE VIH VIH VIL 022598 3/9 DS2064 TIMING DIAGRAM: WRITE CYCLE 1 tWC ADDRESSES VIH VIL VIH VIL VIH VIL tAW CE VIL VIL tWP WE VIH VIL VIL VIH tWR tOEW tODW DOUT tDS VIH DIN VIL SEE NOTES 2, 3, 4, 5, 6 AND 7 tDH VIH DATA IN STABLE VIL 022598 4/9 DS2064 TIMING DIAGRAM: WRITE CYCLE 2 tWC VIH ADDRESSES VIL tAW CE VIH VIL VIL VIH tWP VIH VIL tWR VIH VIL VIH WE VIL VIL tCOE tODW DOUT tDS VIH DIN VIL SEE NOTES 2, 3, 4, 5, 6 AND 7 tDH VIH DATA IN STABLE VIL TIMING DIAGRAM: DATA RETENTION - POWER UP, POWER DOWN VCC DATA RETENTION MODE 2.7V VIH tCDR tR VCC - 0.2V VIL CE GND SEE NOTE 8 022598 5/9 DS2064 DATA RETENTION CHARACTERISTICS PARAMETER Data Retention Supply Voltage Data Retention Current at 5.5V Data Retention Current at 2.0V Chip Deselect to Data Retention Recovery Time * Typical values are at 25C SYMBOL VDR ICCR1 ICCR2 tCDR tR CONDITIONS CE1 > VCC - 0.5V CE1 > VCC - 5.0V CE1 > VCC - 5.0V 0 2 MIN 2.0 0.1* 50* TYP (tA=-40C to +85C) MAX 5.5 1 750 UNITS V A nA s ms FUNCTION TABLE MODE READ WRITE DESELECT STANDBY STANDBY CE1 L L L H X CE2 H H H X L OE L X H X X WE H L H X X A0 - A12 STABLE STABLE X X X DQ - DQ7 DATA OUT DATA IN HIGH-Z HIGH-Z HIGH-Z POWER ICCO ICCO ICCO ICCS ICCS 022598 6/9 DS2064 NOTES: 1. WE is high for read cycles. 2. OE = VIH or VIL. If OE = VIH during write cycle, the output buffers remain in a high impedance state. 3. tWP is specified as the logical AND of CE and WE. tWP is measured from the latter of CE or WE going low to the earlier of CE or WE going high. 4. tDH and tDS are measured from the earlier of CE or WE going high. 5. If the CE low transition occurs simultaneously with or latter than the WE low transition, the output buffers remain in a high impedance state. 6. If the CE high transition occurs prior to or simultaneously with the WE high transition, the output buffers remain in a high impedance state. 7. If WE is low or the WE low transition occurs prior to or simultaneously with the CE low transition, the output buffers remain in a high impedance state. 8. If the VIH level of CE is 2.0V during the period that VCC voltage is going down from 4.5V to 2.7V, ICCS1 current flows. DC TEST CONDITIONS Outputs Open All voltages are referenced to ground AC TEST CONDITIONS Output Load: 100 pF + 1TTL Gate Input Pulse Levels: 0V - 3.0V Timing Measurement Reference Levels Input: 1.5V Output: 1.5V Input Pulse Rise and Fall Times: 5 ns 022598 7/9 DS2064 DS2064 28-PIN DIP PKG DIM B D A IN. MM B IN. MM 1 A C IN. MM D IN. MM E IN. MM C F IN. MM G IN. MM H IN. MM J IN. MM K IN. MM J 28-PIN MIN 1.440 30.99 0.540 13.72 0.140 3.56 0.590 14.99 0.015 0.380 0.110 2.79 0.090 2.29 0.625 15.88 0.008 0.20 0.015 0.38 MAX 1.460 32.00 0.560 14.22 0.160 4.06 0.625 15.88 0.040 1.02 0.135 3.43 0.110 2.79 0.675 17.15 0.012 0.30 0.021 0.53 F K G E H 022598 8/9 DS2064 DS2064S 28-PIN SOIC PKG DIM A IN. MM A1 IN. MM b IN. MM C IN MM D IN. MM e IN. MM E1 IN. MM H IN MM L IN MM MIN 28-PIN MAX 0.120 3.05 0.014 0.35 0.020 0.50 0.0125 0.32 0.728 18.50 0.080 2.04 0.002 0.05 0.012 0.30 0.004 0.10 0.697 17.70 0.050 BSC 1.27 BSC 0.324 8.23 0.453 11.5 0.016 0.40 0 0.350 8.90 0.500 12.7 0.051 1.30 10 a The chamfer on the body is optional. If it is not present, a terminal 1 identifier must be positioned so that 1/2 or more of its area is contained in the hatched zone. 022598 9/9 |
Price & Availability of DS2064
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